1. Field of the Invention
The present invention relates to an organic electroluminescent display (OELD) device, and more particularly, to a top emission type OELD device including an organic emitting layer having an increasing area and improved luminance and a method of fabricating the same.
2. Discussion of the Related Art
The OELD device as a flat panel display device has excellent characteristics, such as high luminance, lower power consumption, and so on. In addition, since the OELD device is a self-emission type, the OELD device has high contrast ratio, a thin profile, a wide viewing angle and fast response time. Moreover, due to their simple fabricating process, the fabrication costs of OELD devices are low as compared with LCD devices.
The OELD devices are divided into a passive matrix type and an active matrix type according to the driving method thereof. The passive matrix type OELD devices have a simple structure and a simple fabricating process. However, the passive matrix type OELD devices have disadvantages of high power consumption and low quality images. Moreover, the more lines are disposed, the less the passive matrix type OELD device has aperture ratio. On the other hand, the active matrix type OELD devices have advantages of high emission efficiency and high quality images.
In the active matrix type OELD device, a thin film transistor for turning on and off a pixel is disposed in each pixel. A first electrode, which is connected to the thin film transistor, is turned on and off, and a second electrode facing the first electrode functions as a common electrode. A voltage applied to the pixel is charged in a storage capacitor. The voltage is applied to the first electrode during corresponding frame due to the storage capacitor. The OELD device can operate in each frame irrespective of a number of scanning lines. As a result, the active matrix type OELD device has advantages, for example, in power consumption, such that the active matrix type OELD device is widely used.
FIG. 1 is a circuit diagram of the related art active matrix type OELD device. In FIG. 1, a gate line GL, a data line DL, a power line PL, a switching thin film transistor (TFT) STr, a driving TFT DTr, a storage capacitor (StgC) and an organic electroluminescent diode E are formed in each pixel region P of the active matrix type OELD device. The gate and data lines GL and DL cross each other to define the pixel region P, and the power line PL for applying a power voltage is parallel to the data line DL.
The switching TFT STr is disposed at a crossing portion of the gate and data lines GL and DL, and the driving TFT DTr is connected to the switching TFT STr. A first electrode of the organic electroluminescent diode E is connected to the driving TFT DTr, and a second electrode of the organic electroluminescent diode E is connected to the power line PL. The storage capacitor StgC is positioned between a gate electrode of the driving TFT DTr and a source electrode of the driving TFT DTr. When the switching TFT STr is turned on by a signal through the gate line GL, a single from the data line DL is applied to the gate electrode of the driving TFT DTr through the switching TFT STr such that the driving TFT DTr is turned on. As a result, the organic electroluminescent diode E emits light. When the driving TFT DTr is turned on, a voltage level applied into the organic electroluminescent diode E is determined such that the organic electroluminescent diode E can produce a predetermined gray scale. Even if the switching TFT STr is turned off, a voltage level applied into the organic electroluminescent diode E is maintained due to the storage capacitor StgC.
The OELD device is classified into a tope emission type and a bottom emission type. The bottom emission type OELD device has problems, for example, low aperture ratio. Accordingly, the top emission type OELD device is widely used.
FIG. 2 is a schematic plan view of one pixel region in the related art top emission type OELD device, and FIG. 3 is a cross-sectional view taken along the line III-III of FIG. 2. For convenience of explanation, each of a switching TFT and a driving TFT is shown as a rectangular box. In FIGS. 2 and 3, the OELD device 1 includes first and second substrates 10 and 70, and a seal pattern (not shown) sealing a spaced between the first and second substrates 10 and 70.
On the first substrate, a gate line 21, a data line 30, a power line 31, a switching TFT STr, a driving TFT DTr, a passivation layer 40, an organic emitting diode E and a bank 50 are formed. The gate and data lines 21 and 30 cross each other to define a pixel region P, and the power line 31 is parallel to the data line 30. The switching TFT STr is connected to the gate and data lines 21 and 30. The driving TFT DTr is connected to the switching TFT and the power line 31, and the passivation layer 40 including a drain contact hole 43, which exposes a portion of the driving TFT DTr, is formed on the driving TFT DTr. The organic electroluminescent diode E includes first and second electrodes 47 and 58, and an organic emitting layer 55 therebetween. The first electrode 47 is connected to the driving TFT DTr through the drain contact hole 43. The organic emitting layer 55 includes emitting material patterns of red, green and blue colors. The bank 50 is positioned at boundaries of the pixel region P and has an opening corresponding to an emitting area EA. The organic emitting layer 55 is positioned in the emitting area EA. The second electrode 58 is formed on the organic emitting layer 55 and covers an entire surface of the first substrate 10. The first and second electrodes 47 and 58 respectively provide an electron and a hole into the organic emitting layer 55. The second substrate 70 is spaced apart from the second electrode 58 on the first substrate 10 by the seal pattern.
As mentioned above, the bank 50 is formed at boundaries of the pixel region P and surrounds the emitting area EA. In addition, the bank 50 covers a portion of the first electrode 47 to cover the drain contact hole 43. When the first electrode 47 contacts the driving TFT DTr through the drain contact hole 43, the first electrode 47 has an uneven surface such as a “V” shape. If the organic emitting layer 55 is formed on an uneven surface of the first electrode 47, there is a concentration problem of a current or an electric field such that a thermal degradation is generated and lifetime is reduced. To prevent theses problems, the bank 50 covers the uneven surface of the first electrode 47 corresponding to the drain contact hole 43.
In the above OELD device 1, a size of the emitting area EA depends on a position of the drain contact hole 43. Namely, aperture ratio of the OELD device 1 is determined by a portion of the drain contact hole 43. When the drain contact hole 43 is positioned at an uppermost portion or at lowest portion of a pixel region P, the aperture ration of the OELD device 1 can be maximized. Unfortunately, it is almost impossible to position the drain contact hole 43 at an uppermost portion or at lowest portion of a pixel region P. Consequently, there is a limitation for maximizing the aperture ratio of the OELD device 1.